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SVEditor
Details Group Tabs
Date | Ranking | Installs | Clickthroughs |
---|---|---|---|
January 2023 | 246/671 | 70 (0.02%) | 13 |
December 2022 | 308/805 | 50 (0.01%) | 19 |
November 2022 | 335/808 | 49 (0.01%) | 13 |
October 2022 | 264/811 | 82 (0.02%) | 23 |
September 2022 | 310/812 | 58 (0.01%) | 20 |
August 2022 | 267/808 | 71 (0.02%) | 17 |
July 2022 | 260/816 | 82 (0.02%) | 20 |
June 2022 | 305/810 | 58 (0.01%) | 17 |
May 2022 | 314/810 | 60 (0.01%) | 24 |
April 2022 | 289/817 | 74 (0.02%) | 21 |
March 2022 | 424/820 | 31 (0.01%) | 24 |
February 2022 | 647/819 | 4 (0%) | 13 |
Unsuccessful Installs in the last 7 Days: 0
Download last 500 errors (CSV)Friday, January 27, 2023 - 12:10
Reviews Sign in to post reviews
Currently not installable
Submitted by G L on Tue, 2022-02-08 06:18
SV Editor is currently not installable because bintray.com returns a bad gateway error.
Outliner -> is it possible to customize?
Submitted by Just Just on Wed, 2017-05-31 10:44
I also prefer to be able to customize the Outline pannel - for example to add Verilog Named Blocks. Is it possible?
Real nice Verilog editor
Submitted by Tobias Binkowski on Fri, 2015-08-28 04:01
That's a real nice thing - whenever I have not tested it so much by now.
I'm missing one feature:
(System)Verilog knows named blocks, eg:
always @(*) begin : MY_REAL_COOL_BLOCK
/* Do stuff */
end
Would be really cool when this name could be displayed in the Outline as it is done for module-instance names.
Thanks for the great work!
Best free Verilog / System Verilog editor out there
Submitted by Stevenaz Mising name on Wed, 2012-05-02 02:01
Kudos to Matthew for all the hard work he has put into, and continues to put into this editor. I am using it at work, and a number of my colleagues at work are also starting to use it.
Keep up the good work Matt.
(Full disclosure: I have fixed a handfull of bugs, but Matthew has done all the real work here)