SVEditor provides a development environment for SystemVerilog, Verilog, and VHDL files. It features syntax coloring, structure display, content assist, and source formatting.
Categories: Editor, IDE, Languages, Source Code Analyzer
Tags: Verilog, SystemVerilog, System Verilog, HVL, UVM, OVM, VMM, VHDL
Additional Details
Eclipse Versions: 2022-03 (4.23), 2021-12 (4.22), 2021-09 (4.21), 2021-06 (4.20), 2021-03 (4.19), 2020-12 (4.18), 2020-09 (4.17), 2020-06 (4.16), 2020-03 (4.15), 2019-12 (4.14), 2019-09 (4.13), 2019-06 (4.12), 2019-03 (4.11), 2018-12 (4.10), 2018-09 (4.9), Photon (4.8), Oxygen (4.7), 2022-06 (4.24), 2022-09 (4.25), 2022-12 (4.26), 2023-03 (4.27), 2023-06 (4.28), 2023-09 (4.29), 2023-12 (4.30), 2024-03 (4.31), 2024-06 (4.32), 2024-09 (4.33), 2024-12 (4.34), 2025-03 (4.35)
Platform Support: Windows, Mac, Linux/GTK
Organization Name: Matthew Ballance
Development Status: Beta
Date Created: Sunday, February 7, 2010 - 20:30
License: EPL
Date Updated: Tuesday, April 21, 2015 - 11:21
Submitted by: Matthew Ballance
| Date | Ranking | Installs | Clickthroughs |
|---|---|---|---|
| January 2025 | 333/631 | 17 | 6 |
| December 2024 | 256/654 | 50 | 6 |
| November 2024 | 327/658 | 27 | 9 |
| October 2024 | 268/663 | 52 | 7 |
| September 2024 | 290/642 | 41 | 7 |
| August 2024 | 278/641 | 37 | 28 |
| July 2024 | 267/663 | 47 | 10 |
| June 2024 | 318/681 | 36 | 12 |
| May 2024 | 299/682 | 41 | 10 |
| April 2024 | 301/687 | 42 | 11 |
| March 2024 | 283/694 | 57 | 5 |
| February 2024 | 278/687 | 51 | 10 |
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Reviews Add new review
Currently not installable
Submitted by G L on Tue, 02/08/2022 - 06:18
SV Editor is currently not installable because bintray.com returns a bad gateway error.
Outliner -> is it possible to customize?
Submitted by Just Just on Wed, 05/31/2017 - 10:44
I also prefer to be able to customize the Outline pannel - for example to add Verilog Named Blocks. Is it possible?
Real nice Verilog editor
Submitted by Tobias Binkowski on Fri, 08/28/2015 - 04:01
That's a real nice thing - whenever I have not tested it so much by now.
I'm missing one feature:
(System)Verilog knows named blocks, eg:
always @(*) begin : MY_REAL_COOL_BLOCK
/* Do stuff */
end
Would be really cool when this name could be displayed in the Outline as it is done for module-instance names.
Thanks for the great work!
Best free Verilog / System Verilog editor out there
Submitted by stevenaz Mising name on Wed, 05/02/2012 - 02:01
Kudos to Matthew for all the hard work he has put into, and continues to put into this editor. I am using it at work, and a number of my colleagues at work are also starting to use it.
Keep up the good work Matt.
(Full disclosure: I have fixed a handfull of bugs, but Matthew has done all the real work here)