SVEditor
Details Group Tabs
Date | Ranking | Installs | Clickthroughs |
---|---|---|---|
March 2021 | 271/572 | 5 (0.03%) | 0 |
February 2021 | 317/911 | 79 (0.02%) | 17 |
January 2021 | 341/930 | 69 (0.02%) | 24 |
December 2020 | 297/919 | 93 (0.02%) | 14 |
November 2020 | 290/925 | 105 (0.02%) | 26 |
October 2020 | 287/927 | 112 (0.02%) | 13 |
September 2020 | 289/894 | 95 (0.02%) | 16 |
August 2020 | 299/867 | 71 (0.02%) | 12 |
July 2020 | 267/870 | 100 (0.02%) | 18 |
June 2020 | 288/867 | 92 (0.02%) | 17 |
May 2020 | 300/876 | 93 (0.02%) | 18 |
April 2020 | 263/891 | 139 (0.03%) | 20 |
March 2020 | NA | 0 (0%) | 24 |
Unsuccessful Installs in the last 7 Days: 1
Count | Error Message |
---|---|
1 | Cannot complete the install because one or more required items could not be found.... |
Monday, March 1, 2021 - 20:16
Reviews Sign in to post reviews
Outliner -> is it possible to customize?
Submitted by Just Just on Wed, 2017-05-31 10:44
I also prefer to be able to customize the Outline pannel - for example to add Verilog Named Blocks. Is it possible?
Real nice Verilog editor
Submitted by Tobias Binkowski on Fri, 2015-08-28 04:01
That's a real nice thing - whenever I have not tested it so much by now.
I'm missing one feature:
(System)Verilog knows named blocks, eg:
always @(*) begin : MY_REAL_COOL_BLOCK
/* Do stuff */
end
Would be really cool when this name could be displayed in the Outline as it is done for module-instance names.
Thanks for the great work!
Best free Verilog / System Verilog editor out there
Submitted by Stevenaz Mising name on Wed, 2012-05-02 02:01
Kudos to Matthew for all the hard work he has put into, and continues to put into this editor. I am using it at work, and a number of my colleagues at work are also starting to use it.
Keep up the good work Matt.
(Full disclosure: I have fixed a handfull of bugs, but Matthew has done all the real work here)