Design and Verification Tools (DVT) IDE for e, SystemVerilog, and VHDL 3.5.16

Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL and is similar to well-known programming tools like Visual Studio®, NetBeans®, and IntelliJ®.

It comprises an IEEE standard-compliant parser, a smart code editor, an intuitive GUI, and a comprehensive set of features that help with code inspection, navigation, documentation, and debugging and an innovative linting framework. Since it is built on the Eclipse Platform, DVT can be easily integrated within a large plug-in ecosystem.

DVT allows design and verification engineers to overcome the limitations of plain text editors and use a modern and powerful tool that enables them to:

• Increase the speed and quality of new code development
• Easily understand complex source code
• Simplify the maintenance of legacy code and reusable libraries
• accelerate language and methodology learning

Some of the features that DVT offers include:

• Autocomplete
• Compilation errors signaled on the fly
• In-line reminders for task tracking (TO DOs)
• Customizable code and project templates
• Hyperlinks that helps navigate faster in the source code
• Semantic search
• Refactoring
• Macro expansion
• Class and structural browsing
• Trace port connections
• UML diagrams for inspecting and documenting the architecture
• Module flow diagrams for inspecting and documenting a module structure
• Automated documentation extraction
• UVM support and compliance checking
• Cross-language capabilities for mixed-language projects

DVT integrates with all major simulators, revision control systems like CVS, Git, Subversion, and ClearCase and bug tracking systems such as Bugzilla and ClearQuest.

You can read more in the DVT Datasheet.

Snapshots:
- e Language
- SystemVerilog
- VHDL

Demo Movies:
- Demo Movies