Design and Verification Tools - E, SystemVerilog, VHDL 3.3.7

The Design and Verification Tools (DVT) plugin is a powerful and modern, yet easy to use programming environment for the e language, SystemVerilog and VHDL. It enables faster and smarter code development and simplifies legacy code maintenance for novices and experts alike.

The DVT plug-in is similar to well-known programming tools like VisualC and IntelliJ. A unified window combines the smart editor with the syntax checker, linter, class browser, methodology compliance checking, task tracking, dynamic UML diagrams, and more.

Engineers can use the editor's hyper-links, auto-complete, in-line documentation, semantic search, and smart-log viewer features. Therefore, they do not have to switch out from the editor to the simulator, browser or console and can stay focused on their code writing or verification work. As a result, the speed and quality of code development increase significantly.

You can read more in the DVT Datasheet.

The complete feature matrix may be found at DVT Features.

Snapshots:
- e Language
- SystemVerilog
- VHDL

Demo Movies:
- Demo Movies